Date posted 05/14/2026 Category Engineering Hire Type Employee Job ID 16907 Base Salary Range $229000-$343000 Remote Eligible No Date Posted 05/14/2026 We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have built your career in digital design where execution determines silicon success. You understand the difference between RTL that synthesizes cleanly and code that creates downstream timing problems. You have closed timing on multi-GHz datapaths, resolved clock domain crossing issues, and made power versus performance tradeoffs that define successful products.High-speed interconnect is your domain. You understand SerDes and die-to-die links, sub-nanosecond latency requirements, and reliable link training logic. You still review critical RTL because that is where decisions are made. When timing reports show violations, you identify root cause. At Synopsys, you will lead digital design for interconnect solutions enabling AI systems to scale.What You'll Be DoingLead digital design for high-speed die-to-die interconnect ICs from microarchitecture through physical design handoffDirect RTL development, logic synthesis, timing closure, and clock domain crossing verificationOversee DFT implementation including scan insertion, ATPG, MBIST, and boundary scanManage verification strategy, testbench architecture, assertion-based verification, and coverage closureGuide pre-silicon validation using emulation platforms for link training and error recovery testingConduct technical reviews of microarchitecture, RTL quality, synthesis QoR, and verification plansThe Impact You Will HaveYou will establish RTL architecture and implementation methodology for interconnect IPs enabling next-generation AI systemsYour synthesis and timing strategies will determine whether designs meet frequency targets within power budgetsThe verification infrastructure you develop will impact first-silicon success and reduce debug cyclesYour DFT architecture will influence test coverage, yield learning, and production test economicsYour technical decisions on clock architecture and datapath optimization will affect product competitivenessWhat You'll Need15+ years digital design experience with multiple high-speed ASIC tapeouts, including 5+ years in technical leadershipStrong expertise in SystemVerilog RTL design including complex FSMs, pipelined datapaths, and clock domain crossingDemonstrated experience with logic synthesis and timing closure on multi-GHz designsProven background in high-speed digital design for SerDes, PHY, or die-to-die interconnectComprehensive DFT experience including scan design, ATPG, MBIST, and boundary scanSolid foundation in digital verification including UVM, assertions, and formal verificationWho You AreYou analyze timing reports and distinguish architectural issues from transient concernsYou evaluate verification plans for completeness, identifying gaps in corner case coverageYou assess RTL for synthesis implications, recognizing structures that create timing or area challengesYou make informed tradeoffs between latency, throughput, power, and area based on requirementsYou have developed engineers in metastability handling, gray code crossing, and low-latency optimizationThe Team You'll Be Part OfYou will lead the digital design organization within Silicon Engineering, focused on high-bandwidth, ultra-low-latency die-to-die links for AI compute and networking systems. The team covers RTL design, logic synthesis, timing closure, DFT, digital verification, emulation, and program execution. You will work with analog design on PHY interfaces, physical implementation on timing closure, and system architects on protocol and performance requirements.#LI-SW1 At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.